1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC), and more particularly, to a scan flip-flop for a multi-threshold voltage CMOS circuit.
2. Description of the Related Art
In order to increase the integration of a semiconductor device, demands for a low power consumption semiconductor IC have gradually increased. An effective method for implementing a low power consumption semiconductor IC is reducing power supply voltage. However, reducing the power supply voltage causes lowered speeds of transistors. To solve this problem, a multi-threshold voltage CMOS IC that comprises a MOS transistor having a low threshold voltage and a MOS having a high threshold voltage is used.
FIG. 1 is a diagram of the structure of an ordinary multi-threshold voltage CMOS (MTCMOS) circuit. The MTCMOS circuit 10 shown in FIG. 1 is disclosed in an article, “A 1-V Multi-threshold-Voltage CMOS Digital Signal Processor for Mobile Phone Application” of S. Mutoh et al., 1996, IEEE JSSC, Vol. 31, No. 11, pp. 1795-1802.
Referring to FIG. 1, the MTCMOS circuit 10 comprises MOS switches Q1 and Q2 that are serially connected between power source (VDD or GND) and a logic circuit 12. These MOS switches Q1 and Q2 have relatively high threshold voltage Vth. The MOS switches Q1 and Q2 are turned on when the circuit 10 operates (that is, the circuit 10 is in an active mode), and provide power source voltage to the logic circuit 12 having a relatively low threshold voltage. When the circuit 10 does not operate (that is, the circuit 10 is in a sleep mode), the MOS switches Q1 and Q2 are turned off such that power source voltage is not provided to the logic circuit 12. Thus, the leakage current (for example, sub-threshold current, etc.) of the logic circuit 12 decreases such that the power consumption of the entire system is minimized. Accordingly, the MTCMOS technology is very effectively used in reducing power consumption of large scale integration (LSI) circuits for portable devices in which sleep mode intervals are much longer than active mode intervals. However, the MTCMOS technology causes loss of data stored in latches or flip-flops of the logic circuit when the power is turned off.
To solve this problem, new technologies, such as a balloon flip-flip, auto backgate controlled (ABC)-MTCMOS, a virtual power/ground rail clamp (VRC), and a complementary pass-transistor flip-flop (CPFF), have been proposed. Among these, the CPFF technology, which was disclosed in Korean Patent Application No. 10-2001-0029730 filed by the present applicant on May 29, 2001, enables the MTCMOS to have better quality than other flip-flops in chip area, speed, and power consumption. In particular, the CPFF circuit needs neither a surplus data storage space for storing data in a sleep mode, nor any timing control. In addition, the CPFF has a smaller clock load and a smaller layout area such that high integration of the CPFF is enabled.
However, since the above circuits do not consider design for test (DFT) in their design stage, the circuits cannot apply a clocked-scan function in which a test is performed after receiving a clock signal dedicated for a scan-chain.
Accordingly, as described above, needed is a scan flip-flop having a new structure for an MTCMOS, which can provide the clocked-scan function while maintaining an optimal circuit structure and performance for an MTCMOS.